Embeddedxen中断初始化


xen中的中断初始化--和Linux的差不太多

typedef struct irqdesc {
 char   *type;

 irq_handler_t  handle;

 struct irqchip  *chip;

 struct irqaction  *action;

 unsigned int  flags;

 unsigned int  status;

 spinlock_t  lock;

 void   *chipdata;

 void   *data;

 unsigned int  disable_depth;

 /* Is this one of HID interrupts? */

 unsigned int  isHIDirq;

}irqdesc_t __cacheline_aligned; 

xen/arch/arm/hypervisor/irq.c

 


struct irqdesc irq_desc[NR_IRQS]; //128

 

 


void __init xen_init_IRQ(void)

{

 int irq;

 for (irq = 0; irq < NR_IRQS; irq++)
  irq_desc[irq].status |= IRQ_NO_REQUEST | IRQ_NO_PROBE;


#ifdef CONFIG_SMP
 bad_irq_desc.affinity = CPU_MASK_ALL;

 bad_irq_desc.cpu = smp_processor_id();

#endif


 xen_init_arch_irq();

}

xen/arch/arm/mach-pxa/mainstone.c

 

void __init xen_init_arch_irq(void)

{

 int irq;

 printk("Initing arch-IRQ...\n");
 pxa_init_irq();

 /* setup extra Mainstone irqs */

 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {/*160--175*/


  set_irq_chip(irq, &mainstone_irq_chip);
  set_irq_handler(irq, level_irq_handler);

  if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))

   set_irq_flags(irq, IRQF_VALID | IRQF_TRIGGER_PROBE ); //| IRQF_TRIGGER_NO_AUTO_ENABLE);

  else

   set_irq_flags(irq, IRQF_VALID | IRQF_TRIGGER_PROBE);

 }

 set_irq_flags(MAINSTONE_IRQ(8), 0);

 set_irq_flags(MAINSTONE_IRQ(12), 0);


 MST_INTMSKENA = 0;
 MST_INTSETCLR = 0;


 set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
 set_irq_type(IRQ_GPIO(0), IRQT_RISING);


}

 xen/arch/arm/mach-pxa/irq.c


void __init pxa_init_irq(void)

{

 int irq;

 /* disable all IRQs */
 ICMR = 0;

 /* all IRQs are IRQ, not FIQ */
 ICLR = 0;

 /* clear all GPIO edge detects */
 GFER0 = 0;

 GFER1 = 0;

 GFER2 = 0;

 GRER0 = 0;

 GRER1 = 0;

 GRER2 = 0;

 GEDR0 = GEDR0;

 GEDR1 = GEDR1;

 GEDR2 = GEDR2;

#ifdef CONFIG_PXA27x
 /* And similarly for the extra regs on the PXA27x */

 ICMR2 = 0;

 ICLR2 = 0;

 GFER3 = 0;

 GRER3 = 0;

 GEDR3 = GEDR3;

#endif

 /* only unmasked interrupts kick us out of idle */
 ICCR = 1;

 /* GPIO 0 and 1 must have their mask bit always set */
 GPIO_IRQ_mask[0] = 3;

 //NR_IRQS=512
 //PXA_IRQ_SKIP=0

 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {

  set_irq_chip(irq, &pxa_internal_chip_low);

  set_irq_handler(irq, level_irq_handler);

  set_irq_flags(irq, IRQF_VALID);

 }

#if PXA_INTERNAL_IRQS > 32
 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {

  set_irq_chip(irq, &pxa_internal_chip_high);

  set_irq_handler(irq, level_irq_handler);

  set_irq_flags(irq, IRQF_VALID);

 }

#endif

 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
  set_irq_chip(irq, &pxa_low_gpio_chip);

  set_irq_handler(irq, edge_irq_handler);

  set_irq_flags(irq, IRQF_VALID | IRQF_TRIGGER_PROBE);

 }

 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
  set_irq_chip(irq, &pxa_muxed_gpio_chip);

  set_irq_handler(irq, edge_irq_handler);

  set_irq_flags(irq, IRQF_VALID | IRQF_TRIGGER_PROBE);

 }

 /* Install handler for GPIO>=2 edge detect interrupts */
 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);

 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);

}

 以上是xen中的中断初始化分析。下面看一下DOM的中断初始化。在DOM中，实际上没有了中断的概念，全部被evtchn_desc_t所替代了。

 

DOM

 

arch/arm/kernel/traps-xen.c

void __init trap_init(void)
{

 //unsigned long vectors = CONFIG_VECTORS_BASE;
 unsigned long vectors = (unsigned long) __guestvectors;//.extern __guestvectors  arch/arm/kernel/entry-armv-xen.S

 extern char __stubs_start[], __stubs_end[];

 extern char __vectors_start[], __vectors_end[];

 extern char __kuser_helper_start[], __kuser_helper_end[];

 int kuser_sz = __kuser_helper_end - __kuser_helper_start;

 /*
  * Copy the vectors, stubs and kuser helpers (in entry-armv.S)

  * into the vector page, mapped at 0xffff0000, and ensure these

  * are visible to the instruction stream.

  */

 memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);

 memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);

 memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);

 /*
  * Copy signal return handlers into the vector page, and

  * set sigreturn to be a pointer to these.

  */

 memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,

        sizeof(sigreturn_codes));

/* (GCD) From Samsung */
#if 0

 flush_icache_range(vectors, vectors + PAGE_SIZE);

 modify_domain(DOMAIN_USER, DOMAIN_CLIENT);

#endif /* 0 */

}


static evtchn_desc_t evtchn_desc[NR_IRQS];//512

 

 

void __init init_IRQ(void)

{

 int i;

 int cpu;

 spin_lock_init(&irq_mapping_update_lock);

 init_evtchn_cpu_bindings();

 /* No VIRQ or IPI bindings. */
 for (cpu = 0; cpu < NR_CPUS; cpu++) {

  for (i = 0; i < NR_VIRQS; i++)

   per_cpu(virq_to_irq, cpu)[i] = -1;

  for (i = 0; i < NR_IPIS; i++)

   per_cpu(ipi_to_irq, cpu)[i] = -1;

 }

 /* No event-channel -> IRQ mappings. */
 for (i = 0; i < NR_EVENT_CHANNELS; i++) {

  evtchn_to_irq[i] = -1;

  mask_evtchn(i); /* No event channels are 'live' right now. */

 }

 /* No IRQ -> event-channel mappings. */
 for (i = 0; i < NR_IRQS; i++)

  irq_info[i] = IRQ_UNBOUND;

 /* Dynamic IRQ space is currently unbound. Zero the refcnts. */
 for (i = 0; i < NR_DYNIRQS; i++) {

  irq_bindcount[dynirq_to_irq(i)] = 0;

  evtchn_desc[dynirq_to_irq(i)].status  = IRQ_DISABLED;
  evtchn_desc[dynirq_to_irq(i)].action  = NULL;

  evtchn_desc[dynirq_to_irq(i)].depth   = 1;

  evtchn_desc[dynirq_to_irq(i)].handler = &dynirq_type;

  evtchn_desc[dynirq_to_irq(i)].lock = __SPIN_LOCK_UNLOCKED(evtchn_desc->lock);

 }

 /* Phys IRQ space is statically bound (1:1 mapping). Nail refcnts. */
 for (i = 0; i < NR_PIRQS; i++) {

  irq_bindcount[pirq_to_irq(i)] = 1;

  evtchn_desc[pirq_to_irq(i)].status  = IRQ_DISABLED;
  evtchn_desc[pirq_to_irq(i)].action  = NULL;

  evtchn_desc[pirq_to_irq(i)].depth   = 1;

  evtchn_desc[pirq_to_irq(i)].handler = &pirq_type;

  evtchn_desc[pirq_to_irq(i)].lock = __SPIN_LOCK_UNLOCKED(evtchn_desc->lock);

 }

}

 


typedef struct hw_interrupt_type hw_irq_controller;

 

struct hw_interrupt_type {
 const char *typename;

 unsigned int (*startup)(unsigned int irq);

 void (*shutdown)(unsigned int irq);

 void (*enable)(unsigned int irq);

 void (*disable)(unsigned int irq);

 void (*ack)(unsigned int irq);

 void (*end)(unsigned int irq);

 void (*set_affinity)(unsigned int irq, cpumask_t dest);

 int (*set_type)(unsigned int irq, unsigned int type);

 void (*release)(unsigned int irq, void *dev_id);

};

 


typedef struct evtchn_desc {
 hw_irq_controller *handler;

 void *handler_data;

 struct irqaction *action; /* IRQ action list */

 unsigned int status; /* IRQ status */

 unsigned int depth; /* nested irq disables */

 unsigned int irq_count; /* For detecting broken interrupts */

 unsigned int irqs_unhandled;

 spinlock_t lock;

#if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE)

unsigned int move_irq; /* Flag need to re-target intr dest*/

#endif

} evtchn_desc_t;

 

 

 

 

评论

发表评论

此博客中的热门博文

Linux/ARM Page Table Entry 属性设置分析

图片
注：该博文写的比较凌乱，需要以后再修改。 Linux 的页表项总体可以划分为两部分，一部分是物理映射地址，另一部分是对物理地址对应的访问属性。在Linux/ARM的Kernel中，为各式各样的内存属性与定义了一下条目 ：   198 static struct mem_type mem_types[] = {  199         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */  200                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |  201                                   L_PTE_SHARED,  202                 .prot_l1        = PMD_TYPE_TABLE,  203                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,  204                 .domain         = DOMAIN_IO,  205         },  206         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */  207                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,  208                 .prot_l1        = PMD_TYPE_TABLE,  209                 .prot_sect      = PROT_SECT_DEVICE,  210                 .domain         = DOMAIN_IO,  211         },  212         [MT_DEVICE_CACHED] = {    /* iorem
阅读全文

提交了30次才AC －－－【附】POJ 2488解题报告

NND,这道题目，竟然提交了30次，搞的我晕过去了都！花费了将近12个小时！！ 感一下，叹一声！如今的ACM，不仅锻炼编程，还锻炼了心理承受能力！！ 1、注意格式，后面有一个空行 2、注意输出的时候的字典序－－什么叫字典序，要弄清楚 3、注意国际象棋的棋盘－－ 横的是字母，竖的是数字－－ 一定要按照这个格式，否则即使是答案对，也WA 有26次，全部栽在第3点上 3次栽在第二点上 1次栽在第一点上 PS:因为是字典序，所以，可以肯定只需要从（1，1）开始即可。不需要注意那句话：start at any position of the chessboard. Source Code Problem: 2488 User: omycle Memory: 192K Time: 360MS Language: C++ Result: Accepted Source Code #include <iostream> #include <string> using namespace std ; bool ok = false ; int col = 0 ; int row = 0 ; int zoufa [ 8 ][ 2 ]= {{ - 2 ,- 1 } , { - 2 , 1 } , { - 1 ,- 2 } , { - 1 , 2 } , { 1 ,- 2 } , { 1 , 2 } , { 2 ,- 1 } , { 2 , 1 }} ; // int flag [ 50 ][ 50 ]; //第0行的，第零列的全不要 typedef struct { int x ; int y ; } Step ; Step step [ 100 ]; //记录路径呀 Step step_c [ 100 ]; int Count = 0 ; void print ( int n ); //数组比较函数 bool cmpint () { int i = 0 ; while ( i < col * row ) { if ( step_c [ i ]. x < step [ i ]. x ) return false ; //不用 if ( step_c [ i ]. y < step [ i ]
阅读全文

笔记

TUN/TAP:是操作系统内核中的虚拟网络设备。不同于普通靠硬件网路板卡实现的设备，这些虚拟的网络设备全部用软件实现，并向运行与操作系统上的软件提供与硬件的网络设备完全相同的功能。 TUN:等同于一个以太网设备，它操作第二层数据包如以太网数据帧 TAP:模拟了网络层设备，操作第三层数据包比如IP数据封包 操作系统 通过TUN/TAP设备向 绑定该设备的用户空间的程序 发送数据，反之， 用户空间的程序 也可以像操作硬件网络设备那样，通过TNU/TAP设备发送数据。在后种情况下，TUN/TAP设备向 操作系统的网络栈 投递（或“注入”）数据包，从而模拟从外部接受数据的过程。   ------ 基于优先级抢占式调度 ：系统中每个任务都有一个优先级，内核总是将CPU分配给处于就绪态的优先级最高的任务运行。如果系统发现就绪队列中有比当前运行任务更高的优先级任务，就把当前运行任务置于就绪队列中，调入高优先级任务运行。系统采用优先级抢占方式进行调度，可以保证重要的突发事件及时得到处理。
阅读全文