Linux Stuff

xen/arch/arm/kernel/entry-armv.S __vectors_start: swi SYS_ERROR0 /* Reset */ b vector_undefined_instruction + stubs_offset ldr pc,   .LCvswi   + stubs_offset b vector_prefetch_abort + stubs_offset b vector_data_abort + stubs_offset b vector_addrexcptn + stubs_offset b vector_irq + stubs_offset b vector_fiq + stubs_offset .globl __vectors_end __vectors_end: /*  * We group all the following data together to optimise  * for CPUs with separate I & D caches.  */ .align 5 .LCvswi: .word   vector_swi -------------- xen/arch/arm/hypervisor/hypervisor.S ENTRY( vector_swi ) sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} add r8, sp, #S_PC stmdb r8, {sp, lr}^ mrs r8, spsr str lr, [sp, #S_PC] str r8, [sp, #S_PSR] vcpu r8 add r8, r8, #(OFFSET_ARCH_VCPU + OFFSET_GUEST_CONTEXT) ldr r9, [r8, #(OFFSET_SYS_REGS+OFFSET_VPSR)] ldr r10, [sp, #S_SP] cmp r9, #PSR_MODE_USR streq   r10, [r8, #(OFFSET_SYS_REGS+OFFSET_VUSP)] strne   r10, [r8, #(OFFSET_SYS_REGS+OFFSET_VKSP)] ldr     r8, [sp, #S_PSR] bic     r8

1 #include <stdio.h> 2 3 void main() 4 { 5     struct cc{ 6     int a; 7     char *ap; 8     }; 9     struct cc c; 10     c.a=100; 11     c.ap="abcdefg\n"; 12 13     printf("%d;%s",c.a,c.ap); 14 15     struct cc * cp=&c; 16     printf("%d;%s",cp->a,cp->ap); 17 18     struct cc ** cpp=&cp; 19     printf("%d,%s",(**cpp).a,(**cpp).ap); 20     printf("%d,%s",(*cpp)->a,(*cpp)->ap); 21 } 结果： omycle@omycle-desktop:~/network$ ./test 100;abcdefg 100;abcdefg 100,abcdefg 100,abcdefg

xen中的中断初始化--和Linux的差不太多 typedef struct irqdesc {  char   *type;  irq_handler_t  handle;  struct irqchip  *chip;  struct irqaction  *action;  unsigned int  flags;  unsigned int  status;  spinlock_t  lock;  void   *chipdata;  void   *data;  unsigned int  disable_depth;  /* Is this one of HID interrupts? */  unsigned int  isHIDirq; }irqdesc_t __cacheline_aligned;  xen/arch/arm/hypervisor/irq.c   struct irqdesc irq_desc[NR_IRQS]; //128     void __init xen_init_IRQ(void) {  int irq;  for (irq = 0; irq < NR_IRQS; irq++)   irq_desc[irq].status |= IRQ_NO_REQUEST | IRQ_NO_PROBE; #ifdef CONFIG_SMP  bad_irq_desc.affinity = CPU_MASK_ALL;  bad_irq_desc.cpu = smp_processor_id(); #endif  xen_init_arch_irq(); } xen/arch/arm/mach-pxa/mainstone.c   void __init xen_init_arch_irq(void) {  int irq;  printk("Initing arch-IRQ...\n");   pxa_init_irq();  /* setup extra Mainstone irqs */  for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {/*160--175*/   set_irq_chip(irq, &mainston

xenarm中断原理： xenarm项目有两部分构成，一部分是xen,一部分是xenolinux 本文有三部分构成 1.中断初始化 2.中断申请 3.中断响应 -------------------------------------- 中断初始化 xen的irq初始化 : arch/arm/arch-imx21/start.S .b start_xen     | start_xen() //arch/arm/xen/xensetup.c     | platform_setup()----DECLARE_PLATFORM_OP(platform_setup, imx21ads_platform_setup);//arch/arm/arch-imx21/platform.c imx21ads_platform_setup()     | imx21_irq_init() void imx21_irq_init(void) { unsigned int irq; /* Mask all interrupts initially */ IMR(0) = 0; IMR(1) = 0; IMR(2) = 0; IMR(3) = 0; IMR(4) = 0; IMR(5) = 0; for (irq = 0; irq < IMX_IRQS; irq++) { set_irq_chip(irq, &imx21_internal_chip); set_irq_handler(irq, level_irq_handler); set_irq_flags(irq, IRQF_VALID); } for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOF(32); irq++) { set_irq_chip(irq, &imx21_gpio_chip); set_irq_handler(irq, edge_irq_handler); set_irq_flags(irq, IRQF_VALID | IRQF_TRIGGER_PROBE); } set_irq_chained_handle

先看xen的中断申请 申请中断离不开request_irq和setup_irq xen只申请了两个irq一个是timer的,另一个是console. xen/arch/arm/mach-pxa/time.c void __init xen_pxa_timer_init(void) { unsigned long clock_tick_rate; OIER = 0; OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; if (cpu_is_pxa25x()) clock_tick_rate = 3686400; else if (machine_is_mainstone()) clock_tick_rate = 3249600; else clock_tick_rate = 3250000; set_oscr2ns_scale(clock_tick_rate); ckevt_pxa_osmr0.mult = div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); ckevt_pxa_osmr0.min_delta_ns = clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; cksrc_pxa_oscr0.mult = clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); setup_irq (IRQ_OST0, & pxa_ost0_irq ); /* timebase_freq = CLOCK_TICK_RATE: source clock rate in Hz */ //timebase_freq = 1000000LL; timebase_freq = CLOCK_TICK_RATE; system_timer_clocksource = &cksrc_pxa_oscr0; system_timer_clockevent

最初的跳转： arch/arm/kernel/entry-armv.S __irq_svc: svc_entry #ifdef CONFIG_PREEMPT get_thread_info tsk ldr r8, [tsk, #TI_PREEMPT] @ get preempt count add r7, r8, #1 @ increment it str r7, [tsk, #TI_PREEMPT] #endif irq_handler ...  __irq_usr: usr_entry get_thread_info tsk #ifdef CONFIG_PREEMPT ldr r8, [tsk, #TI_PREEMPT] @ get preempt count add r7, r8, #1 @ increment it str r7, [tsk, #TI_PREEMPT] #endif irq_handler .macro irq_handler 1: get_irqnr_and_base r0, r6, r5, lr movne r1, sp @ @ routine called with r0 = irq number, r1 = struct pt_regs * @ adrne lr, 1b bne  asm_do_IRQ 看asm_do_IRQ: xen/arch/arm/hypervisor/irq.c asmlinkage void asm_do_IRQ(unsigned int irq, struct xen_cpu_user_regs *regs) { struct irqdesc *desc; if (irq >= NR_IRQS) { printk("Bad IRQ = %d\n", irq); }   /* (GCD) CONFIG_XEN_BENCHMARK    * GPIO37 irq#69 is decode from interrupt #10 in pxa_gpio_demux_handler() function    * See file xen/arch/arm/mach-pxa/irq.c    */ desc = get_irq_descriptor(irq); desc-> handl